OpenCores
URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] - Rev 7

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
7 no message rherveille 8377d 08h /
6 Added 'timescale to all files
Fixed bug where control registers would always latch data, instead of when addressed
rherveille 8377d 08h /
5 Rewrote some sections. Minor Verilog coding style issues. rherveille 8383d 13h /
4 Fixed some incomplete port lists. Fixed some Verilog related issues.
Design now compiles completely.
rherveille 8384d 18h /
3 Created VHDL & Verilog subdirectories. Moved files accordingly. rherveille 8387d 12h /
2 Initial verilog release rherveille 8387d 13h /
1 Standard project directories initialized by cvs2svn. 8387d 13h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.