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Subversion Repositories axi4_tlm_bfm

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Rev Log message Author Age Path
27 Updated simulation scripts. daniel.kho 3790d 06h /
26 Refactored simulation folders. daniel.kho 3790d 06h /
25 Refactored folders. daniel.kho 3790d 07h /
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3790d 07h /
23 Added top-level user example used in technical paper. daniel.kho 3798d 01h /
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3798d 01h /
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3801d 03h /
20 Updated simulation scripts. daniel.kho 3801d 03h /
19 Updated synthesis constraints and scripts. daniel.kho 3801d 03h /
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3801d 03h /
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3801d 03h /
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3904d 00h /
15 [minor]: cleaned up sources. daniel.kho 3906d 06h /
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3914d 21h /
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3915d 01h /
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3924d 05h /
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3926d 00h /
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3930d 00h /
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3932d 20h /
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4033d 02h /

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