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Rev Log message Author Age Path
42 Major enhancements and bugfix. Used DDR for AXI BFM for enhanced functionality and performance. Tested in simulation; TODO update synthesis design files. daniel.kho 3713d 01h /
41 Updated simulation scripts. daniel.kho 3713d 22h /
40 Added asynchronous reset in tester logic. daniel.kho 3713d 22h /
39 Deprecated symbolsPerTransfer and outstandingTransactions; replaced with lastTransaction. Fixed small bug in BFM; tData and tValid should be valid even for the last transaction. daniel.kho 3724d 09h /
38 Added coverage-driven randomisation to tester. daniel.kho 3724d 09h /
37 Refactored nReset to reset for real hardware. daniel.kho 3743d 22h /
36 Added missing pkg-types.vhdl file for simulation. daniel.kho 3770d 22h /
35 More fixes to Windows script. daniel.kho 3776d 08h /
34 Added double-quotes for Windows script. daniel.kho 3776d 08h /
33 Removed semicolons for Windows script. daniel.kho 3776d 08h /
32 Added compile+simulate script for Windows. daniel.kho 3776d 08h /
31 Added initial Xilinx Vivado synthesis scripts and constraints. daniel.kho 3790d 06h /
30 Refactored synthesis scripts. daniel.kho 3790d 06h /
29 Updated simulation scripts. daniel.kho 3790d 07h /
28 Temporarily remove simulation folder. daniel.kho 3790d 07h /
27 Updated simulation scripts. daniel.kho 3790d 07h /
26 Refactored simulation folders. daniel.kho 3790d 07h /
25 Refactored folders. daniel.kho 3790d 08h /
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3790d 08h /
23 Added top-level user example used in technical paper. daniel.kho 3798d 01h /

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