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Rev Log message Author Age Path
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.
tadejm 7654d 03h /
103 This commit was manufactured by cvs2svn to create tag 'complete_1'. 7656d 17h /
102 Little fixes (to fix warnings). mohor 7656d 17h /
101 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7660d 19h /
100 Synchronization changed. mohor 7660d 19h /
99 PCI_BIST replaced with CAN_BIST. mohor 7660d 19h /
98 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7666d 06h /
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7666d 06h /
96 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7666d 08h /
95 Virtual silicon ram instances added. simons 7666d 08h /
94 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7671d 19h /
93 synthesis full_case parallel_case fixed. mohor 7671d 19h /
92 clkout is clk/2 after the reset. mohor 7672d 03h /
91 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7672d 16h /
90 paralel_case and full_case compiler directives added to case statements. mohor 7672d 16h /
89 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7673d 14h /
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.
mohor 7673d 14h /
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.
mohor 7673d 14h /
86 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7675d 06h /
85 Typo fixed. mohor 7675d 06h /

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