OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] - Rev 125

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
125 Synchronization changed, error counters fixed. mohor 7561d 09h /
124 ALTERA_RAM supported. mohor 7581d 15h /
123 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7588d 21h /
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7588d 21h /
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7588d 21h /
120 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7597d 18h /
119 Artisan RAMs added. mohor 7597d 18h /
118 Artisan RAM fixed (when not using BIST). mohor 7597d 18h /
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7597d 18h /
116 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7603d 12h /
115 Artisan ram instances added. simons 7603d 12h /
114 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7630d 13h /
113 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7630d 13h /
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7630d 13h /
111 Fixed according to the linter.
Case statement for data_out joined.
mohor 7632d 13h /
110 Fixed according to the linter. mohor 7632d 13h /
109 Fixed according to the linter. mohor 7632d 14h /
108 Fixed according to the linter. mohor 7632d 14h /
107 Fixed according to the linter. mohor 7632d 15h /
106 Unused signal removed. mohor 7638d 12h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.