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[/] - Rev 147

Rev	Log message	Author	Age	Path
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7166d 18h	/
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7166d 23h	/
145	Arbitration bug fixed.	igorm	7166d 23h	/
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7313d 15h	/
143	Bit acceptance_filter_mode was inverted.	igorm	7313d 15h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7332d 14h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7332d 14h	/
140	I forgot to thange one signal name.	igorm	7387d 12h	/
139	Signal bus_off_on added.	igorm	7387d 13h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7426d 15h	/
137	Header changed.	mohor	7426d 15h	/
136	Error counters changed.	mohor	7426d 16h	/
135	Header changed.	mohor	7426d 16h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7534d 13h	/
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7541d 00h	/
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7541d 00h	/
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7541d 00h	/
130	mbist signals updated according to newest convention	markom	7541d 00h	/
129	Error counters changed.	mohor	7557d 09h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7557d 09h	/