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Rev	Log message	Author	Age	Path
152	Fixes for compatibility after the SW reset.	igorm	7298d 00h	/
151	When CAN was reset by setting the reset_mode signal in mode register, it was possible that CAN was blocked for a short period of time. Problem occured very rarly.	igorm	7300d 18h	/
150	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7319d 18h	/
149	Fixed synchronization problem in real hardware when 0xf is used for TSEG1.	igorm	7319d 18h	/
148	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7322d 01h	/
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7322d 01h	/
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7322d 06h	/
145	Arbitration bug fixed.	igorm	7322d 06h	/
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7468d 22h	/
143	Bit acceptance_filter_mode was inverted.	igorm	7468d 22h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7487d 21h	/
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7487d 21h	/
140	I forgot to thange one signal name.	igorm	7542d 19h	/
139	Signal bus_off_on added.	igorm	7542d 19h	/
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7581d 22h	/
137	Header changed.	mohor	7581d 22h	/
136	Error counters changed.	mohor	7581d 22h	/
135	Header changed.	mohor	7581d 22h	/
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7689d 20h	/
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7696d 07h	/

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