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Rev Log message Author Age Path
157 In "Extended mode" when dual filter was used and standard frame received,
upper nibble of the data was not filtered ok.		 igorm 7003d 21h /
156 Wake-up interrupt was generated in some cases. igorm 7024d 19h /
155 rd_info_pointer fixed (fifo_empty was used instead of info_empty). igorm 7033d 02h /
154 irq is cleared after the release_buffer command. This bug was entered with
changes for the edge triggered interrupts.		 igorm 7132d 19h /
153 Arbitration capture register changed. SW reset (setting the reset_mode bit)
doesn't work as HW reset.		 igorm 7140d 15h /
152 Fixes for compatibility after the SW reset. igorm 7144d 21h /
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.		 igorm 7147d 16h /
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7166d 15h /
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7166d 15h /
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7168d 22h /
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7168d 22h /
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7169d 03h /
145 Arbitration bug fixed. igorm 7169d 03h /
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7315d 19h /
143 Bit acceptance_filter_mode was inverted. igorm 7315d 19h /
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7334d 18h /
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7334d 18h /
140 I forgot to thange one signal name. igorm 7389d 16h /
139 Signal bus_off_on added. igorm 7389d 17h /
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7428d 19h /

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