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Rev	Log message	Author	Age	Path
46	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7838d 10h	/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7838d 10h	/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7838d 11h	/
43	Directory keeper.	mohor	7838d 18h	/
42	Initial version of the project.	mohor	7838d 18h	/
41	Incomplete sensitivity list fixed.	mohor	7838d 19h	/
40	Typo fixed.	mohor	7838d 19h	/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7838d 20h	/
38	Temporary backup version (still fully operable).	mohor	7840d 10h	/
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7840d 10h	/
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7840d 10h	/
35	Several registers added. Not finished, yet.	mohor	7843d 14h	/
34	Errors monitoring improved. arbitration_lost improved.	mohor	7845d 20h	/
33	abort_tx added.	mohor	7845d 20h	/
32	abort_tx added. Bit destuff fixed.	mohor	7845d 20h	/
31	Wishbone interface added.	mohor	7847d 10h	/
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7847d 19h	/
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7848d 16h	/
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7849d 08h	/
27	This file is not used.	mohor	7853d 17h	/

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