URL https://opencores.org/ocsvn/can/can/trunk

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[/] - Rev 58

Rev	Log message	Author	Age	Path
58	timescale.v is used for simulation only.	mohor	7818d 07h	/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7818d 07h	/
56	Doubled declarations removed.	mohor	7819d 06h	/
55	wire declaration added.	mohor	7819d 06h	/
54	This commit was manufactured by cvs2svn to create tag 'branch-release-1-0'.		7824d 08h	/
53	CAN pins located.	mohor	7824d 08h	/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7824d 08h	/
51	Xilinx RAM added.	mohor	7824d 09h	/
50	Top level signal names changed.	mohor	7824d 09h	/
49	Actel APA ram changed. Now synchronous read is used.	mohor	7828d 00h	/
48	Actel APA ram supported.	mohor	7828d 01h	/
47	Data is latched on read.	mohor	7828d 01h	/
46	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7837d 23h	/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7837d 23h	/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7838d 00h	/
43	Directory keeper.	mohor	7838d 07h	/
42	Initial version of the project.	mohor	7838d 07h	/
41	Incomplete sensitivity list fixed.	mohor	7838d 08h	/
40	Typo fixed.	mohor	7838d 09h	/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7838d 09h	/