OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.
mohor 7773d 21h /
58 timescale.v is used for simulation only. mohor 7774d 08h /
57 Mux used for clkout to avoid "gated clocks warning". mohor 7774d 08h /
56 Doubled declarations removed. mohor 7775d 07h /
55 wire declaration added. mohor 7775d 08h /
54 This commit was manufactured by cvs2svn to create tag 'branch-release-1-0'. 7780d 09h /
53 CAN pins located. mohor 7780d 09h /
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7780d 09h /
51 Xilinx RAM added. mohor 7780d 10h /
50 Top level signal names changed. mohor 7780d 10h /
49 Actel APA ram changed. Now synchronous read is used. mohor 7784d 02h /
48 Actel APA ram supported. mohor 7784d 02h /
47 Data is latched on read. mohor 7784d 02h /
46 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7794d 01h /
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 7794d 01h /
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 7794d 02h /
43 Directory keeper. mohor 7794d 08h /
42 Initial version of the project. mohor 7794d 08h /
41 Incomplete sensitivity list fixed. mohor 7794d 10h /
40 Typo fixed. mohor 7794d 10h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.