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Rev Log message Author Age Path
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7669d 06h /
96 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7669d 07h /
95 Virtual silicon ram instances added. simons 7669d 07h /
94 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7674d 18h /
93 synthesis full_case parallel_case fixed. mohor 7674d 18h /
92 clkout is clk/2 after the reset. mohor 7675d 03h /
91 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7675d 16h /
90 paralel_case and full_case compiler directives added to case statements. mohor 7675d 16h /
89 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7676d 13h /
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.
mohor 7676d 13h /
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.
mohor 7676d 14h /
86 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7678d 05h /
85 Typo fixed. mohor 7678d 05h /
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7679d 12h /
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7679d 13h /
82 Removed few signals. mohor 7679d 14h /
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.
mohor 7679d 14h /
80 Form error was detected when stuff bit occured at the end of crc. mohor 7679d 14h /
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7680d 14h /
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.
mohor 7680d 14h /

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