URL https://opencores.org/ocsvn/copyblaze/copyblaze/trunk

Subversion Repositories copyblaze

[/] - Rev 39

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Rev	Log message	Author	Age	Path
39	DEV: - BUG : pop the stack also at "return I" instruction.	ameziti	4741d 10h	/
38	PRJ: - remove automaticly generated code from svn.	ameziti	4741d 10h	/
37	SIM: - validation of the wishbone timer interrupt access	ameziti	4741d 10h	/
36	SW: - code for testing interruption with wishbone timer.	ameziti	4741d 10h	/
35	PRJ: - remove inversionned files.	ameziti	4742d 00h	/
34	SIM: - wisbone: - add testbench for testing wishbone timer.	ameziti	4742d 00h	/
33	SIM: - add path from script	ameziti	4742d 00h	/
32	SW: - wishbone: - add timer code software	ameziti	4742d 00h	/
31	SIM: - wishbone : - add some docs for "Wishbone Verification" methodology.	ameziti	4742d 14h	/
30	SW: - wishbone : - add asm code for the "wb_timer_08" wishbone validation test - add asm code for the "wb_uart_08" wishbone validation test	ameziti	4742d 14h	/
29	SIM: - wishbone : - add constants value of the address of wg_gpio_08 internal registers	ameziti	4742d 14h	/
28	SW - add asm code for the "wb_gpio_08" wishbone validation test	ameziti	4742d 14h	/
27	SW - add asm code for the "wb_gpio_08" wishbone validation test	ameziti	4742d 14h	/
26		ameziti	4742d 15h	/
25	SIM - add ModelSim scripts for the "wb_gpio_08" wishbone validation test	ameziti	4742d 15h	/
24	SIM - change the names format of ModelSim scripts	ameziti	4742d 15h	/
23	SIM: - test the read wishbone instruction	ameziti	4742d 15h	/
22	DEV: - wishbone : - change the names of significants signals - transport the data from the external component to phase2 write.	ameziti	4745d 07h	/
21	SIM: - test the read wishbone instruction	ameziti	4745d 07h	/
20	SIM - change the path of wishbone components	ameziti	4745d 07h	/

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Subversion Repositories copyblaze

[/] - Rev 39

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