OpenCores
URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] - Rev 10

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
10 This commit was manufactured by cvs2svn to create tag 'arelease'. 5631d 01h /
9 This commit was generated by cvs2svn to compensate for changes in r8, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5631d 01h /
8 *** EMERGENCY BUGFIX ***
- Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
- OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads
from $02FF and $0200, instead of $02FF and $0300)		 fpga_is_funny 5631d 01h /
7 This commit was generated by cvs2svn to compensate for changes in r6, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5631d 02h /
6 *** EMERGENCY BUGFIX ***
- Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
- OP "JMP (indirect)" produced a 65C02 like jump. On 6502 a special case exist
when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from
$02FF and $0200, instead $02FF and $0300)		 fpga_is_funny 5631d 02h /
5 Bugfixes for all relationchips with interrupts BRK, IRQ and NMI.
The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down.
The "B" status flag was never set within BRK.
The relationchip between addresses and data while writing onto the stack was badly misalligned.		 fpga_is_funny 5893d 05h /
4 Corrected HTML files for documentation (change $log$ to $Log$ in all VHDL files in first release) fpga_is_funny 5902d 02h /
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5902d 03h /
2 First Revision
After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile
The CVS history in the VHDL files is fine now.		 fpga_is_funny 5902d 03h /
1 Standard project directories initialized by cvs2svn. 5902d 03h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.