URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

[/] - Rev 34

Rev	Log message	Author	Age	Path
34	add binary test date (only sw_sim now )	simon111	5531d 21h	/
33	improve ledseg controler module	simon111	5532d 09h	/
32	fix a compile error	simon111	5532d 09h	/
31	remove pc execute file	simon111	5532d 10h	/
30	begin vailating on fpga	simon111	5532d 10h	/
29	fix some bugs	simon111	5533d 09h	/
28	create a quartus10 project for test the core	simon111	5533d 09h	/
27	improve makefiles	simon111	5533d 21h	/
26	Added old uploaded documents to new repository.	root	5569d 10h	/
25	Added old uploaded documents to new repository.	root	5570d 02h	/
24	New directory structure.	root	5570d 02h	/
23	testing key_schedule module	simon111	5653d 10h	/
22	decrypt module testbench update	simon111	5693d 09h	/
21	decrypt module passed basicly, it's not good code type	simon111	5693d 09h	/
20	finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why	simon111	5707d 08h	/
19	add a modelsim project to samulate the stream_cypher module	simon111	5707d 08h	/
18	try to add decrypt module (not finished yet)	simon111	5717d 10h	/
17	finish block_decypher module	simon111	5768d 16h	/
16	add the block_perm and block_sbox	simon111	5772d 08h	/
15	finished key_schedule module	simon111	5776d 09h	/