URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 129

Rev	Log message	Author	Age	Path
129	New documentation.	mohor	7420d 18h	/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7423d 02h	/
127	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7426d 02h	/
126	run_sim.scr renamed to run_sim for VATS.	mohor	7426d 02h	/
125	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7427d 22h	/
124	Display for VATS added.	mohor	7427d 22h	/
123	All flipflops are reset.	mohor	7427d 23h	/
122	This commit was manufactured by cvs2svn to create tag 'rel_17'.		7430d 23h	/
121	Port signals are all set to zero after reset.	mohor	7430d 23h	/
120	test stall_test added.	mohor	7431d 01h	/
119	cpu_stall_o activated as soon as bp occurs.	mohor	7431d 02h	/
118	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7432d 22h	/
117	Define name changed.	mohor	7432d 22h	/
116	Data latching changed when testing WB.	mohor	7432d 22h	/
115	More debug data added.	mohor	7433d 02h	/
114	CRC generation iand verification in bench changed.	mohor	7433d 03h	/
113	IDCODE test improved.	mohor	7433d 05h	/
112	dbg_tb_defines.v not used.	mohor	7433d 23h	/
111	Define tap_defines.v added to test bench.	mohor	7433d 23h	/
110	Waiting for "ready" improved.	mohor	7434d 00h	/