OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 131

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
131 Documentation updated. Many missing things added. igorm 7377d 15h /
130 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7419d 14h /
129 New documentation. mohor 7419d 14h /
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.
mohor 7421d 22h /
127 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7424d 21h /
126 run_sim.scr renamed to run_sim for VATS. mohor 7424d 21h /
125 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7426d 18h /
124 Display for VATS added. mohor 7426d 18h /
123 All flipflops are reset. mohor 7426d 18h /
122 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7429d 18h /
121 Port signals are all set to zero after reset. mohor 7429d 18h /
120 test stall_test added. mohor 7429d 21h /
119 cpu_stall_o activated as soon as bp occurs. mohor 7429d 22h /
118 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7431d 18h /
117 Define name changed. mohor 7431d 18h /
116 Data latching changed when testing WB. mohor 7431d 18h /
115 More debug data added. mohor 7431d 22h /
114 CRC generation iand verification in bench changed. mohor 7431d 23h /
113 IDCODE test improved. mohor 7432d 00h /
112 dbg_tb_defines.v not used. mohor 7432d 19h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.