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Rev Log message Author Age Path
18 Reset signals are not combined any more. mohor 8303d 13h /
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8327d 03h /
16 bs_chain_o port added. mohor 8329d 03h /
15 bs_chain_o added. mohor 8329d 04h /
14 Document updated. mohor 8330d 01h /
13 Signal names changed to lowercase. mohor 8330d 04h /
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8331d 05h /
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8352d 00h /
10 First official release 1.0. mohor 8356d 04h /
9 Working version. Few bugs fixed, comments added. mohor 8356d 04h /
8 Asynchronous set/reset not used in trace any more. mohor 8357d 03h /
7 First official release 1.0. mohor 8357d 03h /
6 Minor changes for simulation. mohor 8357d 03h /
5 Trace fixed. Some registers changed, trace simplified. mohor 8358d 00h /
4 Initial official release. mohor 8363d 01h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 8363d 01h /
2 Initial official release. mohor 8363d 01h /
1 Standard project directories initialized by cvs2svn. 8363d 01h /

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