URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 30

Rev	Log message	Author	Age	Path
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8229d 07h	/
29	Document revised and put tp better form.	mohor	8232d 20h	/
28	TDO and TDO Enable signal are separated into two signals.	mohor	8265d 04h	/
27	Warnings from synthesys tools fixed.	mohor	8279d 05h	/
26	Warnings from synthesys tools fixed.	mohor	8279d 05h	/
25	trst signal is synchronized to wb_clk_i.	mohor	8280d 02h	/
24	CRC changed so more thorough testing is done.	mohor	8281d 03h	/
23	Trace disabled by default.	mohor	8287d 05h	/
22	Register length fixed.	mohor	8287d 06h	/
21	CRC is returned when chain selection data is transmitted.	mohor	8288d 01h	/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8289d 04h	/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8301d 05h	/
18	Reset signals are not combined any more.	mohor	8303d 14h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8327d 03h	/
16	bs_chain_o port added.	mohor	8329d 03h	/
15	bs_chain_o added.	mohor	8329d 04h	/
14	Document updated.	mohor	8330d 02h	/
13	Signal names changed to lowercase.	mohor	8330d 05h	/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8331d 05h	/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8352d 01h	/