URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 75

Rev	Log message	Author	Age	Path
75	Simulation files.	mohor	7548d 21h	/
74	Removed.	mohor	7548d 21h	/
73	CRC logic changed.	mohor	7548d 21h	/
72	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7551d 03h	/
71	Mbist support added.	simons	7551d 03h	/
70	A pdf copy of existing doc document.	simons	7558d 05h	/
69	WBCNTL added, multiple CPU support described.	simons	7578d 19h	/
68	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7583d 23h	/
67	Lower two address lines must be always zero.	simons	7583d 23h	/
66	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7584d 23h	/
65	WB_CNTL register added, some syncronization fixes.	simons	7584d 23h	/
64	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7604d 23h	/
63	Three more chains added for cpu debug access.	simons	7604d 23h	/
62	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7632d 23h	/
61	Lapsus fixed.	simons	7632d 23h	/
60	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7632d 23h	/
59	Reset value for riscsel register set to 1.	simons	7632d 23h	/
58	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7633d 01h	/
57	Multiple cpu support added.	simons	7633d 01h	/
56	Revision 1.6. Trst changed to active high !!!. In order to be compliant with the standard, reset needs to be negated on the upper layer.	mohor	7899d 21h	/