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Rev Log message Author Age Path
16 Added bus functional model to write configuration and check written
configuration.
dannori 6168d 07h /
15 Fixed FIFO read/write during one clock cycle.
Added further tests to test read/write during the same clock cycle.
Added explanation of FastBits register to spec.
dannori 6174d 18h /
14 Added information about the fast path bits register. dannori 6175d 11h /
13 Added license header and license file dannori 6175d 17h /
12 last ci did not get the fifo files dannori 6175d 21h /
11 Add fifo and top constellation encoder module. dannori 6175d 21h /
10 Added generic dual port ram file for fifo. dannori 6176d 06h /
9 Added first draft of tone order and constellation encoder dannori 6176d 07h /
8 Moving spec to atuc folder dannori 6176d 07h /
7 Removed OO based source. dannori 6176d 14h /
6 Removed vhdl code dannori 6810d 09h /
5 Updated interface according to specification. Output includes async_fifo now. dannori 7307d 11h /
4 This commit was manufactured by cvs2svn to create tag 'import'. 7321d 12h /
3 first import dannori 7321d 12h /
2 first import dannori 7331d 12h /
1 Standard project directories initialized by cvs2svn. 7331d 12h /

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