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Subversion Repositories eco32

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Rev Log message Author Age Path
314 memory controller simulation 2 hellwig 3217d 13h /
313 memory controller simulation 1 hellwig 3217d 14h /
312 memory controller simulation 0 hellwig 3217d 15h /
311 README updated hellwig 3217d 17h /
310 verilated mc implementation with and without trace hellwig 3218d 13h /
309 multicycle simulation of ECO32, using Verilator hellwig 3219d 13h /
308 multicycle design, suitable for being verilated hellwig 3219d 17h /
307 several tests got duration.dat files hellwig 3220d 07h /
306 tool to show display output added hellwig 3220d 14h /
305 tool to show serial output added hellwig 3220d 15h /
304 Makefile updated hellwig 3223d 02h /
303 multicycle simulation control files added hellwig 3223d 02h /
302 tests updated hellwig 3223d 07h /
301 multicycle simulation source files added hellwig 3223d 14h /
300 memdelay experiment code looking better now hellwig 3223d 14h /
299 s3e-500 dac simulation corrected hellwig 3223d 15h /
298 xsa-xst-3 dac simulation corrected hellwig 3223d 16h /
297 memdelay experiment added hellwig 3223d 17h /
296 memspeed experiment added hellwig 3224d 05h /
295 tests for FPGA implementations hellwig 3224d 16h /

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