URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 117

Rev	Log message	Author	Age	Path
117	Clock mrx_clk set to 2.5 MHz.	mohor	8147d 22h	/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	8147d 22h	/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	8148d 20h	/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	8149d 17h	/
113	RxPointer bug fixed.	mohor	8156d 09h	/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	8156d 23h	/
111	Master state machine had a bug when switching from master write to master read.	mohor	8157d 12h	/
110	m_wb_cyc_o signal released after every single transfer.	mohor	8157d 15h	/
109	Comment removed.	mohor	8157d 16h	/
108	Testbench supports unaligned accesses.	mohor	8225d 01h	/
107	TX_BUF_BASE changed.	mohor	8225d 01h	/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8225d 02h	/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8234d 03h	/
104	FCS should not be included in NibbleMinFl.	mohor	8235d 21h	/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8235d 22h	/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8235d 22h	/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8235d 22h	/
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8235d 22h	/
99	Document revised.	mohor	8242d 21h	/
98	Document revised.	mohor	8242d 21h	/