OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 240

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7877d 12h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7877d 12h /
238 Defines fixed to use generic RAM by default. mohor 7889d 16h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7891d 22h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7891d 22h /
235 rev 4. mohor 7892d 12h /
234 Figure list assed to the revision 3. mohor 7892d 21h /
233 Revision 0.3 released. Some figures added. mohor 7892d 21h /
232 fpga define added. mohor 7897d 16h /
231 Description of Core Modules added (figure). mohor 7899d 17h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7903d 14h /
229 case changed to casex. mohor 7903d 14h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7903d 18h /
227 Changed BIST scan signals. tadejm 7903d 18h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7903d 19h /
225 Some minor changes. tadejm 7903d 19h /
224 Signals for a wave window in Modelsim. tadejm 7903d 21h /
223 Some code changed due to bug fixes. tadejm 7903d 21h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7907d 19h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7907d 19h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.