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Rev Log message Author Age Path
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7888d 03h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7888d 03h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7888d 03h /
238 Defines fixed to use generic RAM by default. mohor 7900d 07h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7902d 12h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7902d 12h /
235 rev 4. mohor 7903d 03h /
234 Figure list assed to the revision 3. mohor 7903d 11h /
233 Revision 0.3 released. Some figures added. mohor 7903d 11h /
232 fpga define added. mohor 7908d 06h /
231 Description of Core Modules added (figure). mohor 7910d 08h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7914d 04h /
229 case changed to casex. mohor 7914d 04h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7914d 08h /
227 Changed BIST scan signals. tadejm 7914d 08h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7914d 10h /
225 Some minor changes. tadejm 7914d 10h /
224 Signals for a wave window in Modelsim. tadejm 7914d 11h /
223 Some code changed due to bug fixes. tadejm 7914d 11h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7918d 09h /

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