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Rev Log message Author Age Path
344 bit 9 in phy control register is self clearing olof 4728d 12h /
343 Address miss should not be asserted on short frames olof 4732d 08h /
342 Added cast to avoid inequality when comparing different data types olof 4732d 08h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4732d 08h /
340 Don't fail if log dir already exists olof 4733d 06h /
339 Added basic support for Icarus Verilog olof 4734d 05h /
338 root 5526d 11h /
337 root 5582d 13h /
336 Added old uploaded documents to new repository. root 5583d 16h /
335 New directory structure. root 5583d 16h /
334 Minor fixes for Icarus simulator. igorm 7031d 18h /
333 Some small fixes + some troubles fixed. igorm 7032d 06h /
332 Case statement improved for synthesys. igorm 7045d 11h /
331 Tests for delayed CRC and defer indication added. igorm 7060d 13h /
330 Warning fixes. igorm 7060d 13h /
329 Defer indication fixed. igorm 7060d 15h /
328 Delayed CRC fixed. igorm 7060d 15h /
327 Defer indication fixed. igorm 7060d 15h /
326 Delayed CRC fixed. igorm 7060d 15h /
325 Defer indication fixed. igorm 7060d 16h /

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