URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] - Rev 31

Rev	Log message	Author	Age	Path
31	no message	fisher5090	6688d 08h	/
30	no message	fisher5090	6716d 07h	/
29	no message	fisher5090	6716d 16h	/
28	First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST.	mvpratt	6719d 03h	/
27	xilinx coregen	fisher5090	6729d 07h	/
26	good edition	fisher5090	6729d 08h	/
25	no message	fisher5090	6729d 08h	/
24	First cut. One of the main culprits for the timing violations.	godzilla	6731d 23h	/
23	First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations.	godzilla	6731d 23h	/
22	First cut. Original code from Easic but add some extra controls.	godzilla	6731d 23h	/
21	First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats. So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.	godzilla	6731d 23h	/
20	First cut. Still need to update the document with design changes.	godzilla	6731d 23h	/
19	First cut.	godzilla	6731d 23h	/
18	works well	fisher5090	6736d 12h	/
17	crc test	fisher5090	6736d 19h	/
16	use counter	fisher5090	6740d 04h	/
15	crc module	fisher5090	6740d 04h	/
14	no more used	fisher5090	6740d 04h	/
13	first commit. not yet ready to compile	mvpratt	6740d 04h	/
12	200MHZ	fisher5090	6741d 13h	/