URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] - Rev 39

Rev	Log message	Author	Age	Path
39	first version	fisher5090	6634d 11h	/
38	deleted	fisher5090	6634d 11h	/
37	no message	fisher5090	6634d 12h	/
36	no message	godzilla	6697d 20h	/
35	no message	godzilla	6700d 20h	/
34	Rewritten code.	godzilla	6700d 20h	/
33	Rewritten code.	godzilla	6700d 20h	/
32	no message	fisher5090	6718d 04h	/
31	no message	fisher5090	6718d 04h	/
30	no message	fisher5090	6746d 03h	/
29	no message	fisher5090	6746d 12h	/
28	First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST.	mvpratt	6748d 23h	/
27	xilinx coregen	fisher5090	6759d 04h	/
26	good edition	fisher5090	6759d 04h	/
25	no message	fisher5090	6759d 04h	/
24	First cut. One of the main culprits for the timing violations.	godzilla	6761d 19h	/
23	First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations.	godzilla	6761d 19h	/
22	First cut. Original code from Easic but add some extra controls.	godzilla	6761d 19h	/
21	First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats. So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.	godzilla	6761d 19h	/
20	First cut. Still need to update the document with design changes.	godzilla	6761d 19h	/