| Rev |
Log message |
Author |
Age |
Path |
| 45 |
Corrected erroneous assignment of "dbg" signal. |
wzab |
2688d 15h |
/ |
| 44 |
Changed design for Kintex 7 based boards (AFCK, KC705) so that
they use the VEXTPROJ environment for VCS friendly project management
(described in http://doi.org/10.1117/12.2247944 ) |
wzab |
2688d 15h |
/ |
| 43 |
Removed latch on "dbg" signal |
wzab |
2688d 15h |
/ |
| 42 |
KC705 design upgraded to Vivado 2016.4
Corrrected indentation in a few files in AFCK design |
wzab |
2688d 20h |
/ |
| 41 |
The AFCK project upgraded to Vivado 2016.4 |
wzab |
2688d 20h |
/ |
| 40 |
The "jumbo frame version" renamed from "experimental" to "stable". |
wzab |
2689d 01h |
/ |
| 39 |
Added receiver2t4 - program allowing to receive data from 4 links simultaneously |
wzab |
3257d 14h |
/ |
| 38 |
In synthesis scripts added waiting, until bitsream is generated... |
wzab |
3289d 00h |
/ |
| 37 |
Added new design for AFCK board, which uses 8 10 Gbps links.
Additionally added I2C control of the AFCK Si57x based clock.
The I2C controller is driven via VIO blocks controlled by JTAG
interface from Vivado Tcl console.
Tcl scripts are in the fpga/src/AFCK/i2c_tools directory.
To configure clock to 156.25MHz, and to route it to links,
change directory to fpga/src/AFCK/i2c_tools and do
"source start_10g_links.tcl".
After the clock is reprogrammed, reconfigure the FPGA again
(it seems, that there is a problem with reseting links after
clock is reconfigured). |
wzab |
3290d 14h |
/ |
| 36 |
Added signals needed to ensure, that Si570/1 chip generates the clock.
Added signals driving the rate select lines in the SFP+ modules high.
Added two XDC files - the first one for FM-S14 in the FMC1
connector, the second one for FM-S14 in the FMC2 connector. |
wzab |
3306d 17h |
/ |
| 35 |
Changed comment in definition of the descriptor record
Updated IP cores in project for KC705 (to Vivado 2014.4) |
wzab |
3409d 17h |
/ |
| 34 |
The "old stable" version moved to separate directory. |
wzab |
3423d 22h |
/ |
| 33 |
Added script for automatic compilation of FADE for AFCK, using Vivado 2014.4 |
wzab |
3426d 02h |
/ |
| 32 |
Added the 4-channel FADE test implementation for the AFCK board. |
wzab |
3426d 07h |
/ |
| 31 |
Added receiver2t_cmd to the Makefile |
wzab |
3430d 20h |
/ |
| 30 |
Corrected error which slows down handling of user commands (the thread
executing the user command used wait_event_timeout instead of
wait_event_timeout_interruptiple).
Added demo program which tests time of execution of the user's
command. |
wzab |
3430d 20h |
/ |
| 29 |
Fixed two mistakes in mutex management (mutex not unlocked, when function leaved after an error)
Fixed dead URL in comments. |
wzab |
3435d 21h |
/ |
| 28 |
Correction of an obvious mistake in the Linux driver, which lead to deadlock
when two applications (or two threads) tried to open the same FADE device. |
wzab |
3439d 20h |
/ |
| 27 |
Added file fade_one_channel, allowing to implement multiple FADE instances in a single FPGA. |
wzab |
3454d 04h |
/ |
| 26 |
Corrected small bug in CRC update in eth_sender8,vhd
Added counter of retransmitted packets.
Some minor changes in delay update parameters. |
wzab |
3488d 15h |
/ |
