OpenCores
URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] - Rev 46

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
46 Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. edn_walter 4470d 15h /
45 1. optimized area, by removing unused registers.
2. optimized timing, by removing latches.
edn_walter 4471d 06h /
44 Updated TSU testbench. edn_walter 4471d 09h /
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4472d 07h /
42 Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. edn_walter 4472d 13h /
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4472d 14h /
40 Release version 1.1 edn_walter 4472d 18h /
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.
edn_walter 4472d 18h /
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.
edn_walter 4473d 15h /
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4473d 19h /
36 TSU testbench is now self-checking. Test result is reported at end of simulation. edn_walter 4474d 14h /
35 Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. edn_walter 4475d 13h /
34 Added LGPL file header to all copyrighted files. edn_walter 4475d 16h /
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4475d 17h /
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4475d 19h /
31 Added hand-shaking for the TSU data reading. edn_walter 4476d 13h /
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4476d 13h /
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4476d 13h /
28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 4476d 19h /
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4476d 19h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.