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Rev Log message Author Age Path
178 Added FP math support to support library
Uses code lifted from old version of GNU libc, no adaptation needed
NEEDS testing!		 ja_rd 4776d 11h /
177 Modified 'Adventure' demo to use new support code ja_rd 4776d 12h /
176 Modified 'hello' to use new support code
NOTE: the 'OPCODE EMULATOR' mentioned below is the TRAP HANDLER
The SW opcode emulation has been working for months		 ja_rd 4776d 12h /
175 Updated support library
Removed spurious dependence to accursed '_impure_ptr'		 ja_rd 4776d 12h /
174 started to add branch emulation to opcode emulator ja_rd 4776d 12h /
173 New version of support code, still incomplete. ja_rd 4776d 12h /
172 Added new version of support code, still incomplete ja_rd 4778d 03h /
171 CPU bug fix: MFC0 instructions aborted by privilege trap should not modify any register ja_rd 4779d 05h /
170 Fixed bug in optional emulation of EXT, INS ja_rd 4779d 15h /
169 Fixed bug in emulation of CLO instruction
Added support for simulated hardware IRQs (incomplete)		 ja_rd 4779d 15h /
168 Updated 'opcodes' simulation script to NOT use simulated mips32 instructions and trap instead (as the real CPU does) ja_rd 4779d 15h /
167 Updated simulation script for 'hello' sample: now uses function call log.
It is useless in this demo, but it shows how to use it.		 ja_rd 4779d 17h /
166 Modified simulator, added some debug functionality:
- Optional emulation of some MIPS32r2 opcodes
- Function call trace log using map file (crude implementation)

Plus a few small bug fixes		 ja_rd 4779d 17h /
165 Added (very early draft, very incomplete) reserved opcode trap handler.
Updated opcode tester to test some emulated mips32 opcodes using the trap handler.		 ja_rd 4785d 01h /
164 Minor typo fixes in source file ja_rd 4785d 01h /
163 SW simulator update:
Better disassembly format (hastily tested)
New parameters: start address, breakpoint address, whether or not to trap reserved opcodes		 ja_rd 4785d 02h /
162 Fixed stupid mistake in headers (date of project) ja_rd 4785d 17h /
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4785d 17h /
160 BUG FIX: the cache init code was messing the BSS initialization ja_rd 4786d 19h /
159 bug detected but not fixed in cpu
(1st instruction after entering user mode is executed in kernel mode)		 ja_rd 4787d 02h /

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