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Subversion Repositories ion

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Rev	Log message	Author	Age	Path
37	functions added to package for standard address decoding	ja_rd	4899d 01h	/
36	pre-generated simulation test bench TB1 updated for compatibility to other changes	ja_rd	4899d 01h	/
35	CPU mem_wait logic updated to work with cache	ja_rd	4899d 01h	/
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4899d 01h	/
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4899d 01h	/
32	slite: catch 1-instruction endless loops now can run unattended; will stop at the end of main()	ja_rd	4899d 02h	/
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4899d 02h	/
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4900d 22h	/
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4900d 23h	/
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4900d 23h	/
27	SW simulator updated: now supports CP0 cause register and traps in delay slots	ja_rd	4901d 00h	/
26	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4901d 04h	/
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4901d 04h	/
24	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4901d 04h	/
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	4901d 04h	/
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	4902d 01h	/
21	Converted multiplier module reset to synchronous	ja_rd	4902d 12h	/
20	Updated file list	ja_rd	4902d 12h	/
19	Updated main doc after adding multiplier Fixed some glaring errors and typos	ja_rd	4902d 12h	/
18	pre-generated simulation test bench 'hello world' adapted to new mult module	ja_rd	4902d 14h	/

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Subversion Repositories ion

[/] - Rev 37

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