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Rev	Log message	Author	Age	Path
95	BUG FIX: cache stub properly handles all kind of cycles now	ja_rd	4929d 09h	/
94	Pregenerated demo 'hello' files updated	ja_rd	4929d 09h	/
93	SW simulator supports 'log trigger address' and keyboard input as simulated UART RX. Project parameters now launch adventure demo automatically	ja_rd	4929d 09h	/
92	'hello' demo updated to use new startup files	ja_rd	4929d 09h	/
91	FIX: startup files can now be used to run from FLASH or BRAM	ja_rd	4929d 09h	/
90	Added 'Adventure' demo to be run from the DE-1 FLASH	ja_rd	4929d 09h	/
89	Added startup and utility functions for 'bare metal' applications running from FLASH, plus linker file	ja_rd	4929d 09h	/
88	Added UART RX interface to MPU template	ja_rd	4929d 09h	/
87	Added UART RX interface to MPU template	ja_rd	4929d 09h	/
86	Adapted TB template to use log trigger address	ja_rd	4929d 09h	/
85	BUG FIX: log2 function was wrong	ja_rd	4929d 09h	/
84	Added 'trigger address' for file logging to both the vhdl TB and the python script	ja_rd	4929d 09h	/
83	BUG FIX: LHU was not doing sign extension properly BUG FIX: SLTIU decoding was wrong	ja_rd	4929d 09h	/
82	bug fix: SLTI wasn't working properly in some cases	ja_rd	4931d 09h	/
81	Added a wait state to the SRAM area for the DE-1 demo code	ja_rd	4938d 04h	/
80	Stub cache fixed Now supports code refills from static 16- and 8- bit memory Plus many mirror corrections	ja_rd	4938d 04h	/
79	modelsim wave window script updated	ja_rd	4939d 06h	/
78	Code sample 'memtest' adapted to test read from flash	ja_rd	4939d 06h	/
77	Simulation template now supports simulated flash Synthesis template adapted to latest cache interface Python script now supports simulated flash	ja_rd	4939d 06h	/
76	Adapted pregenerated vhdl files to latest changes	ja_rd	4939d 07h	/

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[/] - Rev 95

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