OpenCores
URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] - Rev 13

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
13 Corrections in analyzer to handle TDi and historical bytes in ATR and PPS
todo: handle inverse convention
acapola 4853d 06h /
12 pps sequence added to test bench
endOfTx added to TxCore
acapola 4864d 03h /
11 added BSD licence header to files acapola 4864d 06h /
10 communication direction probe added acapola 4864d 08h /
9 parity convention fixed acapola 4870d 04h /
8 acapola 4872d 03h /
7 - rx/tx use "cyclesPerEtu" input
- "stopBit" status bit timing fixed
- analyzer: "lastByte" and "bytesCnt" functional
acapola 4873d 03h /
6 analyzer added to test bench, not functional yet... acapola 4874d 03h /
5 draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself) acapola 4875d 03h /
4 Basic test bench completed for T=0: a card send ATR, reader send a command
TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)
acapola 4876d 03h /
3 initial draft, not functional yet acapola 4883d 04h /
2 acapola 4883d 06h /
1 The project and the structure was created root 4884d 02h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.