URL https://opencores.org/ocsvn/m1_core/m1_core/trunk

Subversion Repositories m1_core

[/] - Rev 37

Rev	Log message	Author	Age	Path
37	New scripts for a new Mistral world	fafa1971	5687d 21h	/
36	Added new behavioral stuff for Wishbone peripherals	fafa1971	5687d 21h	/
35	New testbench with Wishbone peripherals	fafa1971	5687d 21h	/
34	Added all the new files for Wishbone peripherals	fafa1971	5687d 21h	/
33	Added files from Mistral's new world	fafa1971	5687d 21h	/
32	Moved files from m1_cpu to m1_core dir	fafa1971	5687d 21h	/
31	New world for Mistral	fafa1971	5687d 21h	/
30	First version with functional verification results.	fafa1971	5764d 19h	/
29	Using code.txt from hello.c	fafa1971	5772d 15h	/
28	Changed NOR operator from (a~\|b) to ~(a\|b)	fafa1971	5772d 20h	/
27	Corrected problems with synthesis and removed system control registers	fafa1971	5778d 19h	/
26	Changed blocking / non-blocking assignments for MUL and DIV requests	fafa1971	5778d 19h	/
25	For now the top-level for synthesis is just m1_cpu	fafa1971	5778d 19h	/
24	Corrected include dirs	fafa1971	5778d 19h	/
23	New script using the correct command file for synthesis with Xilinx ISE WebPack	fafa1971	5778d 19h	/
22	Added script file for synthesis with Xilinx ISE WebPack	fafa1971	5778d 20h	/
21	First revision (you should substitute '~' char with real path).	fafa1971	5785d 13h	/
20	Used only lower bits also for SRAV instruction.	fafa1971	5804d 01h	/
19	Added changes suggested by Paolo Piscopo & Simone Lunardo to fix the bugs they found.	fafa1971	5813d 20h	/
18	Limited range of SHAMT (shift amount) to be only 5 bits ([4:0])	fafa1971	5813d 21h	/