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19 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'. 6590d 11h /
18 Minor fixes. This release is FPGA proven. mikel262 6590d 11h /
17 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'. 6612d 08h /
16 Documentation update, minor fixes mikel262 6612d 08h /
15 Redesigned. Fully pipelined, always ready for data design mikel262 6612d 09h /
14 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'. 6616d 08h /
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6616d 08h /
12 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'. 6617d 08h /
11 changed ROM memory model to synchronous mikel262 6617d 08h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6618d 09h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6620d 20h /
8 Updated DOC mikel262 6620d 20h /
7 documentation update. minor area optimization. mikel262 6621d 07h /
6 minor updates mikel262 6622d 07h /
5 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_1'. 6622d 09h /
4 area optimization - 100 slices less mikel262 6622d 09h /
3 This commit was manufactured by cvs2svn to create tag 'MDCT_B10'. 6622d 21h /
2 Initial import (Beta Release) mikel262 6622d 21h /
1 Standard project directories initialized by cvs2svn. 6622d 21h /

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