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22 project released under LGPL mikel262 5579d 09h /
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5579d 10h /
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5579d 10h /
19 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'. 6604d 06h /
18 Minor fixes. This release is FPGA proven. mikel262 6604d 06h /
17 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'. 6626d 02h /
16 Documentation update, minor fixes mikel262 6626d 02h /
15 Redesigned. Fully pipelined, always ready for data design mikel262 6626d 03h /
14 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'. 6630d 02h /
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6630d 02h /
12 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'. 6631d 02h /
11 changed ROM memory model to synchronous mikel262 6631d 02h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6632d 04h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6634d 15h /
8 Updated DOC mikel262 6634d 15h /
7 documentation update. minor area optimization. mikel262 6635d 01h /
6 minor updates mikel262 6636d 02h /
5 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_1'. 6636d 03h /
4 area optimization - 100 slices less mikel262 6636d 03h /
3 This commit was manufactured by cvs2svn to create tag 'MDCT_B10'. 6636d 15h /

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