OpenCores
URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

[/] - Rev 26

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
26 Added old uploaded documents to new repository. root 5582d 00h /
25 Added old uploaded documents to new repository. root 5582d 13h /
24 New directory structure. root 5582d 13h /
23 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_8'. 5584d 19h /
22 project released under LGPL mikel262 5584d 19h /
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5584d 20h /
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5584d 20h /
19 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'. 6609d 16h /
18 Minor fixes. This release is FPGA proven. mikel262 6609d 16h /
17 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'. 6631d 12h /
16 Documentation update, minor fixes mikel262 6631d 12h /
15 Redesigned. Fully pipelined, always ready for data design mikel262 6631d 13h /
14 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'. 6635d 12h /
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6635d 12h /
12 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'. 6636d 12h /
11 changed ROM memory model to synchronous mikel262 6636d 12h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6637d 14h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6640d 01h /
8 Updated DOC mikel262 6640d 01h /
7 documentation update. minor area optimization. mikel262 6640d 11h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.