OpenCores
URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] - Rev 15

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
15 Just minor test bench update, syncing all the files. rudi 8244d 12h /
14 Minor fixes to testbench ... rudi 8246d 11h /
13 Fixed Register reads
Tightened up timing for register rd/wr
rudi 8284d 10h /
12 Changed Reset to be active high and async. rudi 8294d 12h /
11 *** empty log message *** rudi 8307d 23h /
10 Fixed the TMS register setup to be tight and correct. rudi 8316d 11h /
9 Many fixes for minor bugs that showed up in gate level simulations. rudi 8316d 11h /
8 - Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
- Removed "Refresh Early" configuration
rudi 8339d 05h /
7 Added Directory Tree Description to README file rudi 8342d 05h /
6 Added Memory controller spec rudi 8351d 04h /
5 *** empty log message *** rudi 8351d 05h /
4 1) Changed Directory Structure
2) Fixed several minor bugs
rudi 8351d 05h /
3 This commit was manufactured by cvs2svn to create tag 'start'. 8428d 03h /
2 Created Directory Structure rudi 8428d 03h /
1 Standard project directories initialized by cvs2svn. 8428d 03h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.