URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] - Rev 141

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Rev	Log message	Author	Age	Path
141	Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days.	rfajardo	4731d 05h	/
140	Including required modules for verilator simulation.	rfajardo	4731d 06h	/
139	Creating a verilator branche.	rfajardo	4731d 06h	/
138	DIR_TO_INSTALL creation using wizard	ConX.	4731d 18h	/
137	Removing uncomplete support for ml509 and not working support for spartan3e_starter_kit_eth (area constraint cannot be reached).	rfajardo	4732d 05h	/
136	Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo.	rfajardo	4739d 01h	/
135	Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo.	rfajardo	4739d 01h	/
134	run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench.	rfajardo	4746d 05h	/
133	Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again. Applying Rubén Diez patch to avoid warnings on firmware load for simulation.	rfajardo	4746d 06h	/
132	ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.	rfajardo	4750d 02h	/
131	Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.	rfajardo	4750d 02h	/
130	minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined.	rfajardo	4750d 04h	/
129	Removing bugs introduced when splitting clocks and reset. 1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v). 2) wait for reset on minsoc_bench.v to assert design_ready	rfajardo	4750d 15h	/
128	Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.	rfajardo	4750d 16h	/
127	Removing redundant simulation output.	rfajardo	4750d 22h	/
126	Updating information about simulation time for Ethernet test.	rfajardo	4750d 22h	/
125	Adjusting testbench messages. Creating tasks for firmware tests.	rfajardo	4750d 23h	/
124	Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.	rfajardo	4751d 00h	/
123	Renaming reg final to firmware_size. Final is a keyword for Verilator.	rfajardo	4751d 05h	/
122	Renaming minsoc-configure.sh to minsoc-setup.sh.	rfajardo	4756d 19h	/

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[/] - Rev 141

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