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Rev Log message Author Age Path
9 Minor code cleanup, changed default BE bit in CP0. ayersg 4237d 11h /
8 Added information for regenerating the BRAM core for the SoC. ayersg 4247d 05h /
7 Corrected functionality of Jal. ayersg 4247d 05h /
6 ayersg 4261d 03h /
5 Added a howto for getting started. ayersg 4262d 08h /
4 Added a howto for getting started. ayersg 4262d 08h /
3 Made whitespace consistent in all Verilog files. ayersg 4264d 10h /
2 Initial release ayersg 4264d 21h /
1 The project and the structure was created root 4265d 21h /

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