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Rev Log message Author Age Path
56 BUF_FIFO redesign, for memory/performance tradeoff mikel262 5305d 12h /
55 mikel262 5316d 13h /
54 mikel262 5316d 13h /
53 mikel262 5316d 13h /
52 Redesigned BUF_FIFO.vhd to significantly reduce area utilization.
Only memory optimized version now possible.
mikel262 5316d 13h /
51 fix in buf fifo (synthesis problem) mikel262 5320d 12h /
50 mikel262 5320d 21h /
49 Added 16 bit RGB 565 input format. mikel262 5320d 21h /
48 mikel262 5320d 22h /
47 mikel262 5320d 22h /
46 x1 mikel262 5330d 00h /
45 stall re-added mikel262 5330d 00h /
44 stall re-added mikel262 5330d 00h /
43 stall readded mikel262 5330d 00h /
42 Added backpressure/stallability of output interface. mikel262 5333d 11h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5470d 23h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5513d 14h /
39 bug fix. mikel262 5516d 12h /
38 Reduced processing latency of Huffman encoding mikel262 5541d 12h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5545d 16h /

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