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Rev Log message Author Age Path
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7208d 19h /
131 Changed "GENERIC" to "DEFAULT" to be Xilinx friendly. rhoads 7208d 19h /
130 Added better spacing rhoads 7208d 19h /
129 Added reset_in to sensitivity list rhoads 7227d 19h /
128 Reset all registers, constants now upper case. rhoads 7346d 06h /
127 This commit was manufactured by cvs2svn to create tag 'V2_1'. 7364d 20h /
126 Added note that CC is for x86 and gmake has problems with MIPS gcc libraries. rhoads 7364d 20h /
125 Fixed pc_source_type comment. rhoads 7364d 20h /
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7364d 20h /
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7431d 20h /
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7495d 21h /
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7507d 09h /
120 Make generics "GENERIC" rhoads 7507d 09h /
119 Opcodes from count.c rhoads 7545d 20h /
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7545d 20h /
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7545d 20h /
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7545d 20h /
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7545d 20h /
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7545d 20h /
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7545d 21h /

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