URL https://opencores.org/ocsvn/mlite/mlite/trunk

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[/] - Rev 20

Rev	Log message	Author	Age	Path
20	Startup code.	rhoads	8340d 01h	/
19	Changed simili run to 40us.	rhoads	8342d 02h	/
18	Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0.	rhoads	8342d 02h	/
17	Fixed "blez $0,target". Made LWL=LW and SWL=SW. Changed tabs to spaces.	rhoads	8342d 02h	/
16	Fixed binary to HEX when the number of digits isn't a multiple of 4.	rhoads	8342d 02h	/
15	Test all MIPS I opcodes.	rhoads	8342d 02h	/
14	Fixed big-endian mode bugs	rhoads	8346d 01h	/
13	Removed reg_bank configuration control	rhoads	8346d 01h	/
12	Better support for dual-port memories, removed old method	rhoads	8346d 01h	/
11	Added comment for DEBUG mode	rhoads	8346d 01h	/
10	Add pause_in to process dependency, fixes "lw $4,0($4)"	rhoads	8346d 01h	/
9	Support for generic_tpram dual-port RAM	rhoads	8351d 05h	/
8	Preparing to use dual-port memory for registers.	rhoads	8352d 02h	/
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8357d 09h	/
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8361d 07h	/
5	This commit was manufactured by cvs2svn to create tag 'Version_1_0'.		8580d 07h	/
4	Update web page	rhoads	8580d 07h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		8580d 08h	/
2	MIPS-lite CPU core	rhoads	8580d 08h	/
1	Standard project directories initialized by cvs2svn.		8580d 08h	/