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Rev Log message Author Age Path
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4228d 07h /
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4232d 04h /
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4233d 00h /
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4233d 03h /
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4233d 04h /
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4233d 07h /
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4233d 08h /
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4233d 13h /
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4233d 13h /
29 added software for generation of test input for the tesbenches JonasDC 4234d 03h /
28 updated makefile for new pipeline sources JonasDC 4234d 03h /
27 test input values for multiplier_tb JonasDC 4234d 03h /
26 testbench for only the montgommery multiplier JonasDC 4234d 03h /
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4234d 03h /
24 changed names of top-level module to mod_sim_exp_core JonasDC 4237d 12h /
23 added descriptive comments JonasDC 4237d 13h /
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4240d 07h /
21 changed x_i signal to xi JonasDC 4241d 15h /
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4241d 15h /
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4246d 10h /

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