| Rev |
Log message |
Author |
Age |
Path |
| 34 |
These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work. |
dgisselq |
2788d 10h |
/ |
| 33 |
Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver. |
dgisselq |
2793d 16h |
/ |
| 32 |
Brought the CPU to its first working version, to include demo. |
dgisselq |
2794d 19h |
/ |
| 31 |
Initial network is now working. Adding CPU control files to repository. |
dgisselq |
2795d 11h |
/ |
| 30 |
Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz. |
dgisselq |
2795d 11h |
/ |
| 29 |
Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator. |
dgisselq |
2823d 08h |
/ |
| 28 |
Including the updates and corrections from the wbuart32 project. |
dgisselq |
2823d 08h |
/ |
| 27 |
Bus changes ... |
dgisselq |
2823d 08h |
/ |
| 26 |
Adjusted the timing comments. |
dgisselq |
2823d 09h |
/ |
| 25 |
The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v. |
dgisselq |
2831d 17h |
/ |
| 24 |
Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board. |
dgisselq |
2850d 12h |
/ |
| 23 |
Includes settings necessary for the Arty to load from flash builds, and to
reconfigure itself later. |
dgisselq |
2860d 11h |
/ |
| 22 |
A useful script for programming the device, given that the current device
program includes a valid comms interface. |
dgisselq |
2860d 12h |
/ |
| 21 |
Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus. |
dgisselq |
2860d 12h |
/ |
| 20 |
Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before. |
dgisselq |
2860d 12h |
/ |
| 19 |
Creates an LED mask portion of writing to the LED's register. Only those
bits specified in the mask (bits [7:4]) will be adjusted in the LED
register on a write. Hence to set all on, set the LED register to 0x0ff,
all off, 0x0f0, or to set LED 0 to on while leaving the others unchanged,
set it to 0x011. |
dgisselq |
2860d 12h |
/ |
| 18 |
The device can now program and configure itself, allowing bootstrap possibilities.
` |
dgisselq |
2860d 12h |
/ |
| 17 |
Fixed the misaddressed I/O peripherals in the fastio peripheral group. In
particular, UART and GPS were misaddressed. This has now been fixed, so these
peripherals (should) match the spec. Further, the default speed of the two
UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the
GPS UART. The Aux UART transmitter also passes testing, so at least that one
works. |
dgisselq |
2862d 11h |
/ |
| 16 |
This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects. |
dgisselq |
2862d 11h |
/ |
| 15 |
These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed. |
dgisselq |
2862d 12h |
/ |
