| Rev |
Log message |
Author |
Age |
Path |
| 37 |
Updated documentation and copyright. |
dgisselq |
2773d 16h |
/ |
| 36 |
Lots of changes, see the git changelog for details. |
dgisselq |
2780d 02h |
/ |
| 35 |
Added comments and copyright notice. |
dgisselq |
2783d 13h |
/ |
| 34 |
These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work. |
dgisselq |
2783d 15h |
/ |
| 33 |
Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver. |
dgisselq |
2788d 21h |
/ |
| 32 |
Brought the CPU to its first working version, to include demo. |
dgisselq |
2790d 00h |
/ |
| 31 |
Initial network is now working. Adding CPU control files to repository. |
dgisselq |
2790d 17h |
/ |
| 30 |
Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz. |
dgisselq |
2790d 17h |
/ |
| 29 |
Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator. |
dgisselq |
2818d 13h |
/ |
| 28 |
Including the updates and corrections from the wbuart32 project. |
dgisselq |
2818d 14h |
/ |
| 27 |
Bus changes ... |
dgisselq |
2818d 14h |
/ |
| 26 |
Adjusted the timing comments. |
dgisselq |
2818d 14h |
/ |
| 25 |
The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v. |
dgisselq |
2826d 22h |
/ |
| 24 |
Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board. |
dgisselq |
2845d 17h |
/ |
| 23 |
Includes settings necessary for the Arty to load from flash builds, and to
reconfigure itself later. |
dgisselq |
2855d 16h |
/ |
| 22 |
A useful script for programming the device, given that the current device
program includes a valid comms interface. |
dgisselq |
2855d 17h |
/ |
| 21 |
Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus. |
dgisselq |
2855d 17h |
/ |
| 20 |
Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before. |
dgisselq |
2855d 17h |
/ |
| 19 |
Creates an LED mask portion of writing to the LED's register. Only those
bits specified in the mask (bits [7:4]) will be adjusted in the LED
register on a write. Hence to set all on, set the LED register to 0x0ff,
all off, 0x0f0, or to set LED 0 to on while leaving the others unchanged,
set it to 0x011. |
dgisselq |
2855d 17h |
/ |
| 18 |
The device can now program and configure itself, allowing bootstrap possibilities.
` |
dgisselq |
2855d 17h |
/ |
