URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 123

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
123	update changelog...	olivier.girard	4638d 14h	/
122	Add coverage report generation (NCVERILOG only) Add support for the ISIM Xilinx simulator.	olivier.girard	4638d 14h	/
121	Add a new FPGA example for the LX9 Microboard from Avnet. Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)	olivier.girard	4710d 14h	/
120	update tools changelog...	olivier.girard	4741d 21h	/
119	Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin.	olivier.girard	4741d 22h	/
118	Changelog update (move to modified BSD license).	olivier.girard	4742d 15h	/
117	To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.	olivier.girard	4742d 15h	/
116	Update documentation to reflect the latest core updates.	olivier.girard	4758d 15h	/
115	Add linker script example.	olivier.girard	4767d 15h	/
114	Improved the VerifyCPU_ID procedure.	olivier.girard	4770d 14h	/
113	Created ChangeLog files...	olivier.girard	4771d 14h	/
112	Modified comment.	olivier.girard	4775d 14h	/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4776d 14h	/
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	4777d 14h	/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4830d 23h	/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4832d 12h	/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4832d 12h	/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4832d 13h	/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4847d 13h	/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4851d 14h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories openmsp430

[/] - Rev 123

Filtering Options