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Rev Log message Author Age Path
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.		 olivier.girard 4587d 16h /
125 update changelog... olivier.girard 4601d 19h /
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.		 olivier.girard 4602d 06h /
123 update changelog... olivier.girard 4623d 17h /
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4623d 17h /
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4695d 18h /
120 update tools changelog... olivier.girard 4727d 01h /
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 4727d 01h /
118 Changelog update (move to modified BSD license). olivier.girard 4727d 18h /
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4727d 18h /
116 Update documentation to reflect the latest core updates. olivier.girard 4743d 19h /
115 Add linker script example. olivier.girard 4752d 18h /
114 Improved the VerifyCPU_ID procedure. olivier.girard 4755d 18h /
113 Created ChangeLog files... olivier.girard 4756d 18h /
112 Modified comment. olivier.girard 4760d 17h /
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4761d 17h /
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4762d 17h /
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4816d 02h /
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4817d 15h /
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4817d 15h /

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