URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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Rev	Log message	Author	Age	Path
145	Add Dhrystone and CoreMark benchmarks to the simulation environment.	olivier.girard	4400d 17h	/
144	Update ChangeLog	olivier.girard	4421d 18h	/
143	Update FPGA software examples to support MSPGCC Uniarch.	olivier.girard	4421d 18h	/
142	Beautify the linker script examples.	olivier.girard	4421d 18h	/
141	Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later)	olivier.girard	4425d 17h	/
140	Update ChangeLog	olivier.girard	4437d 18h	/
139	Add some SVN ignore patterns	olivier.girard	4438d 03h	/
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4438d 03h	/
137	Update ChangeLog	olivier.girard	4469d 17h	/
136	Update all FPGA projects with the latest core version.	olivier.girard	4469d 17h	/
135	Update documentation to reflect the ASIC implementation options.	olivier.girard	4469d 17h	/
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4469d 18h	/
133	Add support for new CPU version.	olivier.girard	4469d 18h	/
132	Update FPGA examples with the POP.B bug fix	olivier.girard	4482d 18h	/
131	Update ChangeLog	olivier.girard	4490d 16h	/
130	Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 )	olivier.girard	4490d 17h	/
129	Update ChangeLog	olivier.girard	4566d 17h	/
128	Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 )	olivier.girard	4566d 17h	/
127	update changelog...	olivier.girard	4602d 17h	/
126	Remove freewrap642 directory. Tools users now have to install TCL/TK instead.	olivier.girard	4602d 17h	/

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[/] - Rev 145

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